DDR 533Mhz, PC4300 SDRAM memory modules

General Information

DDR 533Mhz, PC4300 SDRAM memory modules

DDR SDRAM or double-data-rate synchronous dynamic random access memory is a class of memory integrated circuit used in computers. It achieves greater bandwidth than the preceding single-data-rate SDRAM by transferring data on the rising and falling edges of the clock signal (double pumped). Effectively, it nearly doubles the transfer rate without increasing the frequency of the front side bus. Thus, a system with a 100 MHz front side bus has an effective clock rate of 200 MHz when DDR SDRAM memory is installed. The same system using SDR (single data rate) SDRAM, will not have its front side bus rate doubled and be limited to a 100 MHz front side bus speed. With data being transferred 64 bits at a time, DDR SDRAM gives a transfer rate of [mbcr x 2 x 64] / 8; annotated it looks like this: (memory bus clock rate) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a bus frequency of 100 MHz, DDR-SDRAM gives a max transfer rate of 1600 MB/s. JEDEC has set standards for speeds of DDR SDRAM, divided into two parts: The first specification is for memory chips and the second is for memory modules. The package sizes in which DDR SDRAM is manufactured are also standardised by JEDEC. There is no architectural difference between DDR SDRAM designed for different clock frequencies, e.g. PC-1600 (designed to run at 100 MHz) and PC-2100 (designed to run at 133 MHz). The number simply designates the speed that the chip is guaranteed to run at. Hence DDR SDRAM can be run at lower clock speeds than it was made for (underclocking) or higher clock speeds than it was made for (overclocking). DDR SDRAM DIMMs have 184 pins (as opposed to 168 pins on SDRAM, or, 240 pins on DDR2 SDRAM), and can be differentiated from SDRAM DIMMs by the number of notches (DDR SDRAM has one, SDRAM has two). DDR SDRAM operates at a voltage of 2.5 V, compared to 3.3 V for SDRAM. This can significantly reduce power usage. Note: some DIMMs have nominal voltage of 2.6 V. Many new chipsets use these memory types in dual-channel configurations, which doubles or quadruples the effective bandwidth.

JTF - Just The Facts

Timing	Definition	Abbreviations	What it does
2	CAS Latency	CL	Delay between activation of row and reading of row
3	RAS to CAS (or Row to Column Delay)	tRCD	Activates row
2	Row Precharge Delay (or RAS Precharge Delay)	tRP/tRCP	Deactivates row
6	Row Active Delay (or RAS Active Delay, or time to ready)	tRA/tRD/tRAS	Number of clock cycles between activation and deactivation of row
1	Command Rate	CMD Rate	Delay between chip select and command