DDR3 1866Mhz, PC3-14900 Computer Memory

General Information

DDR3 1866Mhz, PC3-14900 SDRAM memory modules

In electronic engineering, DDR3 SDRAM or double-data-rate three synchronous dynamic random access memory is a random access memory technology used for high speed storage of the working data of a computer or other digital electronic device. It is a part of the SDRAM family of technologies, which is one of many DRAM (dynamic random access memory) implementations, and is an evolutionary improvement over its predecessor, DDR2 SDRAM. Its primary benefit is the ability to run its I/O bus at four times the speed of the memory cells it contains, thus enabling faster bus speeds and higher peak throughputs than earlier technologies. This is achieved at the cost of higher latency. DDR3 memory comes with a promise of a power consumption reduction of 30% compared to current commercial DDR2 modules, due to DDR3's 90 nm fabrication technology, allowing for lower operating currents and voltages (1.5 V, compared to DDR2's 1.8 V or DDR's 2.5 V). "Dual-gate" transistors will be used to reduce leakage of current. The main benefit of DDR3 comes from the higher bandwidth made possible by DDR3's 8 bit deep prefetch buffer, whereas DDR2's is 4 bits, and DDR's is 2 bits deep. Theoretically, these modules could transfer data at the effective clock rate of 800-1600 MHz (using both edges of a 400–800 MHz I/O clock), compared to DDR2's current range of effective 400–800 MHz (200–400 MHz clock) or DDR's range of 200–400 MHz (100–200 MHz). To date, such bandwidth requirements have been mainly found in the graphics market, where fast transfer of information between framebuffers is required. Prototypes were announced in early 2005, and products are appearing on the market as of mid-2007, in the form of motherboards based on Intel's P35 "Bearlake" chipset and memory DIMMs at speeds up to DDR3-1600. AMD's roadmap indicates their own adoption of DDR3 to come in 2008. While electrically incompatible, DDR3 DIMMs have 240 pins, the same number as DDR2, but with a different key notch location.

JTF - Just The Facts

Timing	Definition	Abbreviations	What it does
2	CAS Latency	CL	Delay between activation of row and reading of row
3	RAS to CAS (or Row to Column Delay)	tRCD	Activates row
2	Row Precharge Delay (or RAS Precharge Delay)	tRP/tRCP	Deactivates row
6	Row Active Delay (or RAS Active Delay, or time to ready)	tRA/tRD/tRAS	Number of clock cycles between activation and deactivation of row
1	Command Rate	CMD Rate	Delay between chip select and command