DDR2 900Mhz, PC2-7200 SDRAM memory modules.

General Information

DDR2 900Mhz, PC2-7200 SDRAM memory modules.

In electronic engineering, DDR2 SDRAM or double-data-rate two synchronous dynamic random access memory is a random access memory technology used for high speed storage of the working data of a computer or other digital electronic device. It is a part of the SDRAM (synchronous dynamic random access memory) family of technologies, which is one of many DRAM (dynamic random access memory) implementations, and is an evolutionary improvement over its predecessor, DDR SDRAM. Its primary benefit is the ability to run its bus at twice the speed of the memory cells it contains, thus enabling faster bus speeds and higher peak throughputs than earlier technologies. This is achieved at the cost of higher latency. Like all SDRAM implementations, DDR2 stores memory in memory cells that are activated with the use of a clock signal to synchronize their operation with an external data bus. Like DDR before it, DDR2 cells transfer data both on the rising and falling edge of the clock (a technique called double pumping). The key difference between DDR and DDR2 is that in DDR2 the bus is clocked at twice the speed of the memory cells, so four words of data can be transferred per memory cell cycle. Thus, without speeding up the memory cells themselves, DDR2 can effectively operate at twice the bus speed of DDR. DDR2's bus frequency is boosted by electrical interface improvements, on-die termination, prefetch buffers and off-chip drivers. However, latency is greatly increased as a trade-off. The DDR2 prefetch buffer is 4 bits deep, whereas it is 2 bits deep for DDR and 8 bits deep for DDR3. While DDR SDRAM has typical read latencies of between 2 and 3 bus cycles, DDR2 may have read latencies between 3 and 9 cycles. Because of this higher latency, DDR SDRAM running at the same bus speed as DDR2 is generally considered superior; DDR2 is, however, able to run at substantially higher bus speeds which equates to an overall increase in throughput. Another cost of the increased speed is the requirement that the chips are packaged in a more expensive and more difficult to assemble BGA package as compared to the TSSOP package of the previous memory generations such as DDR and SDRAM. This packaging change was necessary to maintain signal integrity at higher speeds. Power savings are achieved primarily due to an improved manufacturing process through die shrinkage, resulting in a drop in operating voltage (1.8 V compared to DDR's 2.5 V). The lower memory clock frequency may also enable power reductions in applications that do not require the highest available speed.